1. Field of the Invention
This invention relates to semiconductor memory device testing, and more particularly to a method, system, and device for detecting high resistance contacts in semiconductor memory devices.
2. Description of the Related Art
The proliferation of computers and other microprocessor-based devices has contributed to an increasing demand for semiconductor memory. Microprocessors are present not only in computers, but in a diverse range of products including automobiles, cellular telephones and kitchen appliances. A conventional microprocessor executes a sequence of instructions and processes information. Frequently, both the instructions and the information reside in semiconductor memory. Therefore, an increased requirement for memory has accompanied the microprocessor boom.
There are various types of semiconductor memory, including Read Only Memory (ROM) and Random Access Memory (RAM). ROM is typically used where instructions or data must not be modified, while RAM is used to store instructions or data which must not only be read, but modified. ROM is a form of non-volatile storage—i.e., the information stored in ROM persists even after power is removed from the memory. On the other hand, RAM storage is generally volatile, and must remain powered-up in order to preserve its contents.
A conventional semiconductor memory device stores information digitally, in the form of bits (i.e., binary digits). The memory is typically organized as a matrix of memory cells, each of which is capable of storing one bit. The cells of the memory matrix are accessed through the use of column select lines and row select lines. Raising a column select line activates a given column; raising a row select line activates a given row. The bitlines are then used to read from or write to the corresponding cell in the currently active row and column. Memory cells are typically capable of assuming one of two logic states (commonly described as “on” or “off”). Information is stored in the memory by setting each cell in the appropriate logic state. For example, to store a bit having the value “1” in a particular cell, one would set the state of that cell to “on”; similarly, a “0” would be stored by setting the cell to the,“off” state. (The association of “on” with “1” and “off” with “0” is arbitrary, and could be reversed.) Setting a cell to a particular state may require applying a voltage within a corresponding voltage range. For example, “off” may be associated with voltages near circuit ground (“Vss”), while “on” may be associated with voltages near circuit power (“Vcc”).
The two major types of semiconductor RAM, Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM), differ in the manner by which their cells represent the state of a bit. In an SRAM, each memory cell includes transistor-based circuitry that implements a bi-stable latch. A bi-stable latch relies on transistor gain and positive (i.e. reinforcing) feedback to guarantee that it can only assume one of two states—“on” or “off.” The latch is stable in either state (hence, the term “bi-stable”). It can be induced to change from one state, or voltage range, to the other only through the application of an external stimulus; left undisturbed, it will remain in its original state indefinitely. This is just the sort of operation required for a memory circuit, since once a bit value has been written to the memory cell, it will be retained until it is deliberately changed.
In contrast to the SRAM, the memory cells of a DRAM employ a capacitor to store the “on”/“off” logic state (or voltage state) representing the bit. A transistor-based buffer drives the capacitor. The buffer quickly charges or discharges the capacitor to change the state of the memory cell, and is then disconnected. Ideally, the capacitor then holds the charge placed on it by the buffer and retains the stored voltage level. DRAMs have at least two drawbacks compared to SRAMs. The first of these is that leakage currents within the semiconductor memory are unavoidable, and act to limit the length of time the memory cell capacitors can hold their charge. Consequently, DRAMs typically require a periodic refresh cycle to restore sagging capacitor voltage levels. Otherwise, the capacitive memory cells would not maintain their contents. Secondly, changing the state of a DRAM memory cell requires charging or discharging the cell capacitor. The time required to do this depends on the amount of current the transistor-based buffer can source or sink, but generally cannot be done as quickly as a bi-stable latch can change state. Therefore, DRAMs are typically slower than SRAMs. DRAMs offset these disadvantages by offering higher memory cell densities, since the capacitive memory cells are intrinsically smaller than the transistor-based cells of an SRAM.
SRAMs are widely used in applications where speed is of primary importance, such as cache memory supporting the Central Processing Unit (CPU) in a personal computer. Like most semiconductor devices, SRAMs are fabricated en masse on semiconductor wafers, and subsequently sectioned and packaged. In the production process, a wafer sort test is performed. During this step, the individual SRAMs are electrically tested before sectioning the wafer. Any bad SRAMs identified at this stage are discarded when the wafer is sectioned, thus avoiding the cost of packaging.
The wafer sort succeeds in detecting many hard failures, such as shorted address lines. However, there are more subtle defects that can go undetected until the packaged SRAM is subjected to burn-in. Burn-in can include repeatedly writing (and optionally reading) the entire SRAM cell by cell. To further simulate prolonged usage of the device, burn-in may be performed under conditions of increased temperature and/or voltage. High-resistance contacts are among the more subtle defects that may be detected following burn-in. High-resistance contacts are often insufficient to cause the SRAM to fail preliminary functional testing during wafer sort, but tend to worsen after many hours of burn-in. Eventually, the resistance of the contact may be great enough to cause the device to fail when tested after burn-in. Still, some of the devices may pass burn-in yet subsequently fail after actual usage. Clearly, it is extremely undesirable to provide customers with devices that fail prematurely.
It would therefore be desirable to have a means of detecting devices prone to this failure mode before the packaged devices are shipped to customers. It would also be desirable to have a means of detecting these devices before going to the expense and trouble of packaging the devices. Further, it would be desirable to detect these devices before going to the expense of burn-in. Manufacturing costs are reduced and yields are improved the earlier faulty devices are screened.